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Poster
Learning Semantic Representations to Verify Hardware Designs
Shobha Vasudevan · Wenjie (Joe) Jiang · David Bieber · Rishabh Singh · hamid shojaei · C. Richard Ho · Charles Sutton

Thu Dec 09 08:30 AM -- 10:00 AM (PST) @
in Poster Session 6 »

Verification is a serious bottleneck in the industrial hardware design cycle, routinely requiring person-years of effort. Practical verification relies on a "best effort" process that simulates the design on test inputs. This suggests a new research question: Can this simulation data be exploited to learn a continuous representation of a hardware design that allows us to predict its functionality? As a first approach to this new problem, we introduce Design2Vec, a deep architecture that learns semantic abstractions of hardware designs. The key idea is to work at a higher level of abstraction than the gate or the bit level, namely the Register Transfer Level (RTL), which is somewhat analogous to software source code, and can be represented by a graph that incorporates control and data flow. This allows us to learn representations of RTL syntax and semantics using a graph neural network. We apply these representations to several tasks within verification, including predicting what cover points of the design will be exercised by a test, and generating new tests that will exercise desired cover points. We evaluate Design2Vec on three real-world hardware designs, including an industrial chip used in commercial data centers. Our results demonstrate that Design2Vec dramatically outperforms baseline approaches that do not incorporate the RTL semantics, scales to industrial designs, and can generate tests that exercise design points that are currently hard to cover with manually written tests by design verification experts.

Keywords: Deep Learning · Graph Learning

Author Information

Shobha Vasudevan (Google)
Wenjie (Joe) Jiang (Google Brain)

I am currently working in Google Brain, focused on applying deep reinforcement learning to design and optimize accelerator software and hardware systems. Before that, I worked in Google's network analysis and optimization team. I applied a variety of mathematical techniques to solving network optimization problems. I obtained my PhD from Princeton University, where my research focus was on distributed systems, and network optimization.

David Bieber (Google)
Rishabh Singh (Google Brain)
hamid shojaei (Google)
C. Richard Ho (Google)
Charles Sutton (Google)

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