Self-Supervised Graph Representation Learning for chip design-partitioning on multi-FPGA platforms

Integrated circuits (ICs) are used in virtually all electronic equipment’s and have become inseparable parts of modern societies. Due to the continuously shrinking time-to-market, there is a constant need to optimize the various design, validation and manufacturing processes involved in the development of these ICs. Pre-silicon emulation is one such complex process that involves partitioning the design and mapping it on multi-FPGA platforms so that testing and software-development on these chips can be accelerated.We present a novel design-partitioning algorithm that modifies the GAP graph-partitioning architecture (Azade Nazi et. al.) to handle multiple hard-constraints. We then use a constrained greedy algorithm to map the partitions obtained onto the multi-FPGA platform. Our experiments on 3 chip-designs showed either comparable or improved results as compared to the current manual and heuristic-based process. We observe tremendous improvement in the time required to map the design onto the hardware platform which was on an average of 2 minutes as compared to 3-4 weeks required using the manual process.